This invention relates to phase locked loops, and more particularly to phase locked loops operable over a wide dynamic range and having a jitter performance bounded within predetermined limits.
In digital communications, generation of higher rate clock signals from lower rate signals is required frequently. Such clock signals generally need to be generated over wide dynamic ranges of frequency and must be as jitter-free as possible in order to ensure proper data transmission, clock recovery, and synchronization. Digital phase locked loops are most often used to generate stable higher rate clock signals from lower rate clocks. In a digital phase locked loop (DPLL) a digital voltage controlled oscillator (DVCO) fabricates from a very high speed system clock, an output clock signal having a frequency determined by an input control signal. This control signal is derived by comparing the frequency/phase of the input clock and a feedback signal equal to the DVCO output clock divided in frequency by an integer p. By the nature of the feedback loop, the frequency of the output of the DVCO is driven to p times the frequency of the input clock thereby imparting the desired frequency multiplication to the input clock. Disadvantageously, the frequency of the the DVCO will discretely jiggle above and below the desired frequency as repeated comparisons determine that the DVCO frequency needs to be increased or decreased to synchronize the input and feedback signals. The output of the DVCO will thus be a signal that characteristically presents some jitter with respect to an ideal signal operating at the same frequency. Prior art digital phase locked loops which maintain the jitter at a low level generally required complicated implementations. While such implementations have low jitter performance, it is bounded only in a statistical sense. In addition, these prior art phase locked loops have had a limited dynamic range of frequencies over which the circuit would have the desired low jitter performance.
A simple phase locked loop operable over a wide dynamic range of frequencies and which has pre-imposed jitter requirements is therefore desirable for the many digital applications in which a stable clock signal is needed.